Huawei Introduces Tau Scaling Law to Replace Moore’s Law
During the 2026 IEEE International Symposium on Circuits and Systems held in Shanghai, He Tingbo introduced the Tau (τ) Scaling Law, positioning it as a next-generation alternative to the long-standing Moore's Law for advancing semiconductor technology.
Unlike conventional approaches that focus on shrinking transistor dimensions, the Tau Scaling Law centers on time scaling as the primary benchmark for progress. The framework aims to enhance computing performance, energy efficiency, and transistor density by lowering signal transmission delays and reducing overall system execution time.
For many years, semiconductor advancement depended on making transistors smaller to boost processing capability and reduce manufacturing costs. However, physical limitations have made further miniaturization increasingly challenging, while improvements in cost efficiency and performance have slowed considerably.
According to He Tingbo, the Tau Scaling Law introduces a new direction for chip innovation. Huawei is supporting this approach through technologies such as LogicFolding and a layered optimization strategy that integrates devices, circuits, chips, and complete computing systems.
The company’s strategy focuses on lowering transistor and interconnect resistance along with parasitic capacitance to reduce delays at the physical level. Within circuit design, the LogicFolding architecture reorganizes layouts to shorten critical signal routes, decreasing resistive and capacitive burdens while improving both transistor density and circuit efficiency.
At the chip level, Huawei combines software optimization, processor architecture, and silicon engineering to streamline data and instruction flow. This coordinated design increases parallel processing capabilities and cuts total execution time. On the system side, the UnifiedBus interconnect protocol provides unified memory addressing and native memory semantics for SuperPods, helping reduce communication latency in large-scale computing environments.
He noted that Huawei has already incorporated the Tau Scaling framework into smartphones and AI computing platforms. Over the last six years, the company has reportedly developed and mass-produced 381 chips using this methodology across a variety of industries and applications.
Huawei also announced that its upcoming Kirin processors, expected in fall 2026, will be the first to feature the LogicFolding architecture, delivering major improvements in chip performance.
Within industry circles, the Tau Scaling Law has also earned the nickname “He’s Law” in recognition of He Tingbo’s contributions.
Huawei further projects that by 2031, high-end chips created under the Tau Scaling framework could reach transistor densities similar to those expected from 14-angstrom (1.4 nm) manufacturing technologies.
Concluding her presentation, He stressed that cooperation across the semiconductor ecosystem will be critical, emphasizing that no single organization can independently overcome the industry’s future technological challenges.
Unlike conventional approaches that focus on shrinking transistor dimensions, the Tau Scaling Law centers on time scaling as the primary benchmark for progress. The framework aims to enhance computing performance, energy efficiency, and transistor density by lowering signal transmission delays and reducing overall system execution time.
For many years, semiconductor advancement depended on making transistors smaller to boost processing capability and reduce manufacturing costs. However, physical limitations have made further miniaturization increasingly challenging, while improvements in cost efficiency and performance have slowed considerably.
According to He Tingbo, the Tau Scaling Law introduces a new direction for chip innovation. Huawei is supporting this approach through technologies such as LogicFolding and a layered optimization strategy that integrates devices, circuits, chips, and complete computing systems.
The company’s strategy focuses on lowering transistor and interconnect resistance along with parasitic capacitance to reduce delays at the physical level. Within circuit design, the LogicFolding architecture reorganizes layouts to shorten critical signal routes, decreasing resistive and capacitive burdens while improving both transistor density and circuit efficiency.
At the chip level, Huawei combines software optimization, processor architecture, and silicon engineering to streamline data and instruction flow. This coordinated design increases parallel processing capabilities and cuts total execution time. On the system side, the UnifiedBus interconnect protocol provides unified memory addressing and native memory semantics for SuperPods, helping reduce communication latency in large-scale computing environments.
He noted that Huawei has already incorporated the Tau Scaling framework into smartphones and AI computing platforms. Over the last six years, the company has reportedly developed and mass-produced 381 chips using this methodology across a variety of industries and applications.
Huawei also announced that its upcoming Kirin processors, expected in fall 2026, will be the first to feature the LogicFolding architecture, delivering major improvements in chip performance.
Within industry circles, the Tau Scaling Law has also earned the nickname “He’s Law” in recognition of He Tingbo’s contributions.
Huawei further projects that by 2031, high-end chips created under the Tau Scaling framework could reach transistor densities similar to those expected from 14-angstrom (1.4 nm) manufacturing technologies.
Concluding her presentation, He stressed that cooperation across the semiconductor ecosystem will be critical, emphasizing that no single organization can independently overcome the industry’s future technological challenges.
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