During the 2026 IEEE International Symposium on Circuits and Systems held in Shanghai, He Tingbo introduced the Tau (τ) Scaling Law, positioning it as a next-generation alternative to the long-standing Moore's Law for advancing semiconductor technology.

Unlike conventional approaches that focus on shrinking transistor dimensions, the Tau Scaling Law centers on time scaling as the primary benchmark for progress. The framework aims to enhance computing performance, energy efficiency, and transistor density by lowering signal transmission delays and reducing overall system execution time.

For many years, semiconductor advancement depended on making transistors smaller to boost processing capability and reduce manufacturing costs. However, physical limitations have made further miniaturization increasingly challenging, while improvements in cost efficiency and performance have slowed considerably.

According to He Tingbo, the Tau Scaling Law introduces a new direction for chip innovation. Huawei is supporting this approach through technologies such as LogicFolding and a layered optimization strategy that integrates devices, circuits, chips, and complete computing systems.
The company’s strategy focuses on lowering transistor and interconnect resistance along with parasitic capacitance to reduce delays at the physical level. Within circuit design, the LogicFolding architecture reorganizes layouts to shorten critical signal routes, decreasing resistive and capacitive burdens while improving both transistor density and circuit efficiency.

At the chip level, Huawei combines software optimization, processor architecture, and silicon engineering to streamline data and instruction flow. This coordinated design increases parallel processing capabilities and cuts total execution time. On the system side, the UnifiedBus interconnect protocol provides unified memory addressing and native memory semantics for SuperPods, helping reduce communication latency in large-scale computing environments.

He noted that Huawei has already incorporated the Tau Scaling framework into smartphones and AI computing platforms. Over the last six years, the company has reportedly developed and mass-produced 381 chips using this methodology across a variety of industries and applications.

Huawei also announced that its upcoming Kirin processors, expected in fall 2026, will be the first to feature the LogicFolding architecture, delivering major improvements in chip performance.

Within industry circles, the Tau Scaling Law has also earned the nickname “He’s Law” in recognition of He Tingbo’s contributions.

Huawei further projects that by 2031, high-end chips created under the Tau Scaling framework could reach transistor densities similar to those expected from 14-angstrom (1.4 nm) manufacturing technologies.

Concluding her presentation, He stressed that cooperation across the semiconductor ecosystem will be critical, emphasizing that no single organization can independently overcome the industry’s future technological challenges.

Camtek Ltd, a prominent provider of inspection and metrology solutions for the semiconductor sector, announced that it has entered into a final agreement to acquire Visual Layer, an AI-focused firm based in Tel Aviv known for its expertise in visual analytics.

Visual Layer was established by Danny Bickson and Amir Alush and is supported by top Silicon Valley venture capital investors. The company contributes advanced artificial intelligence capabilities, including proprietary technologies and a talented team of AI specialists and software engineers with strong expertise in visual AI. Over the past year, Camtek has collaborated closely with Visual Layer, incorporating its solutions into its own products and working together extensively in research and development, gaining deep familiarity with the company’s technology, personnel, and execution.

Rafi Amit, Camtek’s Chief Executive Officer, stated that AI has been a key strategic focus for the company, and acquiring Visual Layer represents a major advancement in both the scope and speed of its development efforts. He noted that Visual Layer’s technology and team complement Camtek’s ongoing initiatives, and expressed confidence that the acquisition will strengthen the company’s ability to meet the evolving demands of the market. He also highlighted the strong cultural alignment between the two organizations, particularly their shared emphasis on innovation and customer-centricity, reinforced by their year-long collaboration.

Lior Aviram, Executive Chairman of Camtek, added that the semiconductor industry is clearly moving toward AI-powered inspection and metrology solutions, which will shape future competition. He emphasized that Camtek aims to be at the forefront of this shift and expects near-term benefits such as enhanced product performance and efficiency. Additionally, he pointed to opportunities beyond the company’s core business, including the development of AI-driven software and analytics solutions that could generate recurring revenue streams over time.

Danny Bickson, CEO, and Amir Alush, CTO of Visual Layer, commented that semiconductor manufacturing is one of the most complex and strategically significant industries globally, with Camtek playing a central role. They explained that Visual Layer was designed specifically to tackle challenges in industrial visual intelligence, and their collaboration with Camtek over the past year demonstrated how AI can significantly improve production capabilities. Joining Camtek, they said, provides access to broader resources, customers, and scale, enabling greater impact. They also expressed their goal of expanding Camtek’s AI division into a leading center of excellence capable of attracting top-tier talent.

The acquisition is subject to standard closing conditions and is anticipated to be finalized within the coming weeks. Financial details were not disclosed.

Further updates are expected alongside Camtek’s first-quarter 2026 financial results, scheduled for release in May 2026.

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